Memory controllers may convert a series of local user transactions into row and column commands to be sent to a memory device. Reordering memory controllers change the order of these row and column commands in order to improve overall system efficiency and latency
A major challenge in implementing a reordering controller is the need to determine which orderings of memory commands are possible for a given set of transactions. These orderings may be restricted due to: data hazards caused by reads or writes to the same subset of memory addresses; policies instrumented by a user regarding which re-order optimizations are permissible; and other dependencies caused by control commands (such as refresh) or complex commands (such as multicast commands), for example.
Conventional implementations of re-ordering controllers can require checking the above dependencies for each pair of commands in the controller, during each cycle of operation. Such conventional implementations can require significant surface area on a chip to implement, can scale with the square of the number of memory commands in the controller, and because of the relatively large amount of required computation can often be the timing critical path through the memory controller, thus decreasing the frequency at which a memory controller can operate.
An improved reordering memory controller that addresses the above challenges would be desirable.